Job title: RTL Timing (Constraints / Synthesis / STA)
Company: Mobiveil, Inc.
Requirements: Timing (Constraints / Synthesis / STA) Timing ASIC Constraint development , Synthesis / STA. Strong experience in Logic synthesis , STA , Lint and CDC checks , DFT , constraining , physical implementation Hands – on experience in timing analysis Experience in doing SoC level timing analysis Should be familiar with timing analysis for hierarchical designs Familiarity with different types interfaces like PCIe , NVMe / , USB , DDR etc Should be proficient with Synopsys’ Prime Time for timing analysis Good scripting skill in Tcl and Perl Familiarity with different physical design tools knowledge of Synopsys tools Knowledge about data management is a definite plus Good team player working with geo – dispersed cross cultural and cross functional teams Good communication and interpersonal skills required. Educational Qualification BE / BTech or ME / MTech Job Location: Bangalore / Chennai / Hyderaba,
Location: Hyderabad, Telangana – Andhra Pradesh
Job date: Tue, 07 Jan 2020 08:59:46 GMT
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